1. Field of the Invention
The present invention relates to a semiconductor device, and more particularly to pads on a chip for bonding frame leads of a package to the chip.
2. Description of the Prior Art
FIG. 5 is a diagram showing an example of a conventional semiconductor device. As apparent from FIG. 5, on a quadrangular semiconductor chip 2 arranged on a die pad 1, a plurality of pads 3 are disposed along the four sides thereof. Pads 3 are connected with driver circuits 4, 4 which are consisted, for example, of N-channel MOS transistor and P-channel MOS transistor arranged on both sides of pad 3 by printed conductors 5. Also, peripheral circuits 6 are arranged on one side of driver circuit 4.
On the other hand, frame leads 7 made of copper alloy and the like, which will be terminals of packages, are disposed on outside of the die pad 1. Frame leads 7 are connected electrically with the pads 3 by leads 8 made of gold and the like. That is, a single pad 3 on semiconductor chip 2 corresponds to a single lead 7, and each frame lead 7 is made most suitably by taking form and size of the package, magnitude of semiconductor chip 2 and position of the pad 3 into consideration.
Since the conventional semiconductor device is constructed as the above description, when plural types of package are to be used with one type of semiconductor chip 2, for example, if the chip is small in size, frame lead 7 should be long and the tip of lead 7 is to be made thin so as to arrange finely. However, in this case, since there is a case where lead 7 cannot be manufactured in respect with the thickness of the frame, feasible positions and forms of the tip of lead 7 are restricted dependent on each frame. Accordingly, there is a limit to approximate the tip of lead 7 to semiconductor chip 2. Moreover, the length and the angle of the wiring are also limited, so that a frame lead which is optimum for arranging pad 3 cannot be manufactured, and particularly, bonding at the corners of semiconductor chip 2 cannot be performed. In addition, there is the same problem in a case where the molding is performed by decreasing number of terminals without using all pads 3 on semiconductor chip 2.